Massive MIMO detection algorithm and VLSI architecture / Leibo Liu, Guiqiang Peng and Shaojun Wei.
This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to a...
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| Main Authors: | , , |
| Format: | eBook |
| Language: | English |
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Singapore :
Springer,
[2019]
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| Subjects: |
MARC
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| 100 | 1 | |a Liu, Leibo, |e author. |0 http://id.loc.gov/authorities/names/n2006094318 |1 http://isni.org/isni/0000000036865867. | |
| 245 | 1 | 0 | |a Massive MIMO detection algorithm and VLSI architecture / |c Leibo Liu, Guiqiang Peng and Shaojun Wei. |
| 264 | 1 | |a Singapore : |b Springer, |c [2019] | |
| 300 | |a 1 online resource. | ||
| 336 | |a text |b txt |2 rdacontent. | ||
| 337 | |a computer |b c |2 rdamedia. | ||
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| 504 | |a Includes bibliographical references. | ||
| 505 | 0 | |a Intro; Preface; Contents; Abbreviations; 1 Introduction; 1.1 Application Requirements; 1.1.1 Typical Applications in Future; 1.1.2 Communication System Requirements; 1.2 Mobile Communication and MIMO Detection; 1.2.1 Development of Communication Technologies; 1.2.2 Key 5G Technologies; 1.2.3 MIMI Baseband Processing; 1.2.4 Difficulties in Massive MIMO Detection; 1.3 Status Quo of MIMO Detection Chip Research; 1.3.1 ISAP-Based MIMO Detection Chip; 1.3.2 ASIC-Based MIMO Detection Chip; 1.3.3 Limitation of Traditional MIMO Detection Chips. | |
| 505 | 8 | |a 1.4 Dynamic Reconfigurable Chip Technologies of MIMO Detection1.4.1 Overview of Reconfigurable Computing; 1.4.2 Status Quo of Dynamic Reconfiguration Chip of MIMO Detection; References; 2 Linear Massive MIMO Detection Algorithm; 2.1 Analysis of Linear Detection Algorithm; 2.2 Neumann Series Approximation Algorithm; 2.2.1 Algorithm Design; 2.2.2 Error Analysis; 2.2.3 Complexity and Block Error Rate; 2.3 Chebyshev Iteration Algorithm; 2.3.1 Algorithm Design; 2.3.2 Convergence; 2.3.3 Complexity and Parallelism; 2.3.4 Bit Error Rate; 2.3.5 Analysis on Channel Model Impact. | |
| 505 | 8 | |a 2.4 Jacobi Iteration Algorithm2.4.1 Weighted Jacobi Iteration and Convergence; 2.4.2 Complexity and Frame Error Rate; 2.4.3 Analyses on Channel Model Effects; 2.5 Conjugate Gradient Algorithm; 2.5.1 Algorithm Design; 2.5.2 Convergence; 2.5.3 Initial Iteration Value and Search; 2.5.4 Complexity and Parallelism; 2.5.5 Symbol Error Rate; References; 3 Architecture of Linear Massive MIMO Detection; 3.1 NSA-Based Hardware Architecture; 3.1.1 VLSI Top-Level Structure; 3.1.2 Approximate Inversion and Matched Filtering Module; 3.1.3 Equalization and SINR Module; 3.1.4 IFFT and LLR Module. | |
| 505 | 8 | |a 3.1.5 Inverse Module Based on Cholesky Decomposition3.2 Chebyshev Iteration Hardware Architecture; 3.2.1 VLSI Top-Level Structure; 3.2.2 Initial Module; 3.2.3 Iterative Module; 3.2.4 LLR Module; 3.2.5 Experimental Results and Comparison; 3.3 Hardware Architecture Based on Weighted Jacobi Iteration; 3.3.1 VLSI Top-Level Architecture; 3.3.2 Diagonal Systolic Array; 3.3.3 WeJi Module; 3.3.4 LLR Module; 3.3.5 Experimental Result and Comparison; 3.4 Hardware Architecture Based on Conjugate Gradient Method; 3.4.1 VLSI Top-Level Structure; 3.4.2 Input/Output Module; 3.4.3 Multiplication Module. | |
| 505 | 8 | |a 3.4.4 Iterative Module3.4.5 Experimental Results and Comparison; References; 4 Nonlinear Massive MIMO Signal Detection Algorithm; 4.1 Conventional Nonlinear MIMO Signal Detection Algorithm; 4.1.1 ML Signal Detection Algorithm; 4.1.2 SD Signal Detection Algorithm and K-Best Signal Detection Algorithm; 4.2 CHOSLAR Algorithm; 4.2.1 System Model; 4.2.2 QR Decomposition; 4.2.3 Lattice Reduction; 4.2.4 Cholesky Preprocessing; 4.2.5 Improved K-Best Detector and Its Performance Simulation; 4.2.6 Summary and Analysis; 4.3 TASER Algorithm; 4.3.1 System Model; 4.3.2 Semi-definite Relaxation. | |
| 520 | |a This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method. | ||
| 588 | |a Online resource; title from PDF title page (EBSCO, viewed February 22, 2019) | ||
| 650 | 0 | |a MIMO systems. |0 http://id.loc.gov/authorities/subjects/sh2004000485. | |
| 650 | 0 | |a Wireless communication systems. |0 http://id.loc.gov/authorities/subjects/sh92006740. | |
| 650 | 7 | |a MIMO systems. |2 fast |0 (OCoLC)fst01201254. | |
| 650 | 7 | |a Wireless communication systems. |2 fast |0 (OCoLC)fst01176209. | |
| 700 | 1 | |a Peng, Guiqiang, |e author. | |
| 700 | 1 | |a Wei, Shaojun, |e author. | |
| 776 | 0 | 8 | |c Original |z 9811363617 |z 9789811363610 |w (OCoLC)1081001450. |
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