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|a Sharma, Ashok K.
|0 http://id.loc.gov/authorities/names/n96014588
|1 http://isni.org/isni/0000000115936520.
|
| 245 |
1 |
0 |
|a Semiconductor memories
|h [electronic resource] :
|b technology, testing, and reliability /
|c Ashok K. Sharma.
|
| 260 |
|
|
|a Piscataway, N.J. :
|b IEEE Press ;
|a New York :
|b Institute of Electrical and Electronics Engineers,
|c ©1997.
|
| 300 |
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|a 1 online resource (xii, 462 pages) :
|b illustrations.
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|b txt
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|a Includes bibliographical references and index.
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| 505 |
0 |
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|a Preface -- Chapter 1: Introduction -- Chapter 2: Random Access Memory Technologies -- 2.1 Introduction -- 2.2 Static Random Access Memories (SRAMs) -- 2.3 Dynamic Random Access Memories (DRAMs) -- Chapter 3: Nonvolatile Memories -- 3.1 Introduction -- 3.2 Masked Read-Only Memories (ROMs) -- 3.3 Programmable Read-Only Memories (PROMs) -- 3.4 Erasable (UV)-Programmable Read-Only Memories (EPROMs) -- 3.5 Electrically Erasable PROMs (EEPROMs) -- 3.6 Flash Memories (EPROMs or EEPROMs) -- Chapter 4: Memory Fault Modeling and Testing -- 4.1 Introduction ... -- 4.2 RAM Fault Modeling -- 4.3 RAM Electrical Testing -- 4.4 RAM Pseudorandom Testing -- 4.5 Megabit DRAM Testing -- 4.6 Nonvolatile Memory Modeling and Testing -- 4.7 IDDQ Fault Modeling and Testing -- 4.8 Application Specific Memory Testing -- Chapter 5: Memory Design for Testability and Fault Tolerance -- 5.1 General Design for Testability Techniques -- 5.2 RAM Built-in Self-Test (BIST) -- 5.3 Embedded Memory DFT and BIST Techniques -- 5.4 Advanced BIST and Built-in Self-Repair Architectures -- 5.5 DFT and BIST for ROMs -- 5.6 Memory Error-Detection and Correction Techniques -- 5.7 Memory Fault-Tolerance Designs -- Chapter 6: Semiconductor Memory Reliability -- 6.1 General Reliability Issues -- 6.2 RAM Failure Modes and Mechanisms -- 6.3 Nonvolatile Memory Reliability -- 6.4 Reliability Modeling and Failure Rate Prediction -- 6.5 Design for Reliability -- 6.6 Reliability Test Structures -- 6.7 Reliability Screening and Qualification -- Chapter 7: Semiconductor Memory Radiation Effects -- 7.1 Introduction -- 7.2 Radiation Effects -- 7.3 Radiation-Hardening Techniques -- 7.4 Radiation Hardness Assurance and Testing -- Chapter 8: Advanced Memory Technologies -- 8.1 Introduction -- 8.2 Ferroelectric Random Access Memories (FRAMs) -- 8.3 Gallium Arsenide (GaAs) FRAMs -- 8.4 Analog Memories -- 8.5 Magnetoresistive Random Access Memories (MRAMs) -- 8.6 Experimental Memory Devices -- Chapter 9: High-Density Memory Packaging Technologies.
|
| 505 |
8 |
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|a 9.1 Introduction -- 9.2 Memory Hybrids and MCMs (2-D) -- 9.3 Memory Stacks and MCMs (3-D) -- 9.4 Memory MCM Testing and Reliability Issues -- 9.5 Memory Cards -- 9.6 High-Density Memory Packaging Future Directions -- Index.
|
| 546 |
|
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|a English.
|
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|a Semiconductor storage devices.
|0 http://id.loc.gov/authorities/subjects/sh85119900.
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|a Semiconductor storage devices.
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|0 (OCoLC)fst01112182.
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|a IEEE Solid-State Circuits Council.
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|1 http://isni.org/isni/0000000121694564.
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|a Sharma, Ashok K.
|t Semiconductor memories.
|d Piscataway, N.J. : IEEE Press ; New York : Institute of Electrical and Electronics Engineers, ©1997
|z 0780311140
|z 9780780311145
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|w (OCoLC)34281977.
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