A Low Power, High Speed Readout for Pixel Detectors Based on an Arbitration Tree [electronic resource]
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| Format: | Government Document Electronic eBook |
| Language: | English |
| Published: |
Batavia, Ill. : Oak Ridge, Tenn. :
Fermi National Accelerator Laboratory ; Distributed by the Office of Scientific and Technical Information, U.S. Department of Energy,
2019.
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| Abstract: | A low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout, are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allows interleaved latching of data at the output serializer. The design was implemented in a 65 nm LP-CMOS process for the readout of a 64 x 64 pixel array. Measurement results demonstrate a deadtime-less, full frame imaging rate of ̃50 kfps, achieved with a dedicated output for every (32 x 32) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ. |
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| Item Description: | Published through Scitech Connect. 01/01/2019. "fermilab-pub-19-188-ppd" "Other: oai:inspirehep.net:1766999" Fahim, Farah ; Joshi, Siddhartha ; Ogrenci-Memik, Seda ; Mohseni, Hooman ; USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25) |
| Physical Description: | Medium: ED : digital, PDF file. |