Design technology co-optimization in the era of sub-resolution IC scaling [electronic resource] / Lars Liebmann, Kaushik Vaidyanathan, and Lawrence Pileggi.
Tackle the challenges facing the most advanced technology nodes in the microelectronics industry with the help of design technology co-optimization (DTCO). This mediation process aims to ensure competitive technology architecture definition while avoiding schedule or yield risks caused by unrealisti...
Saved in:
| Online Access: |
Full Text (via SPIE Digital Library) |
|---|---|
| Main Authors: | , , |
| Other title: | SPIE digital library. |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Bellingham, Washington :
SPIE,
[2015]
|
| Series: | Tutorial texts in optical engineering ;
v. TT 104. |
| Subjects: |
MARC
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| 505 | 0 | |a 1. The escalating design complexity of sub-resolution scaling -- 2. Multiple exposure patterning enhanced digital logic design -- 3. Design for manufacturability -- 4. Design technology co-optimization (DTCO) -- references. | |
| 520 | |a Tackle the challenges facing the most advanced technology nodes in the microelectronics industry with the help of design technology co-optimization (DTCO). This mediation process aims to ensure competitive technology architecture definition while avoiding schedule or yield risks caused by unrealistically aggressive process assumptions. Find the answers in this Tutorial Text, which reviews the fundamental design objectives as well as the resulting topological constraints of a standard cell logic design flow; cell design, placement, and routing are examined against the backdrop of ever-increasing design constraints in advanced technology nodes. | ||
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