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Low power design with high-level power estimation and power-aware synthesis [electronic resource] / Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla.

Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phon...

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Bibliographic Details
Online Access: Full Text (via Springer)
Main Author: Ahuja, Sumit
Other Authors: Lakshminarayana, Avinash, Shukla, Sandeep K.
Format: Electronic eBook
Language:English
Published: New York, NY : Springer, ©2012.
Subjects:
Low voltage integrated circuits > Design and construction.
Table of Contents:
  • Introduction
  • Related Work
  • Background
  • Architectural Selection using High Level Synthesis
  • Statistical Regression Based Power Models
  • Coprocessor Design Space Exploration Using High Level Synthesis
  • Regression-based Dynamic Power Estimation for FPGAs
  • High Level Simulation Directed RTL Power Estimation
  • Applying Verification Collaterals for Accurate Power Estimation
  • Power Reduction using High-Level Clock-gating
  • Model-Checking to exploit Sequential Clock-gating
  • System Level Simulation Guided Approach for Clock-gating
  • Conclusions.

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