VHDL Modeling for Digital Design Synthesis / by Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin.

VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. Originally introduced as...

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Bibliographic Details

Online Access:	Full Text (via Springer)
Main Author:	Hsu, Yu-Chin
Other Authors:	Tsai, Kevin F., Liu, Jessie T., Lin, Eric S.
Format:	eBook
Language:	English
Published:	Boston, MA : Springer US, 1995.
Subjects:	Engineering. Computer-aided design. Computer engineering. Systems engineering.